1. Field of the Invention
Embodiments of the present invention generally relate to a method and apparatus for reliable processing of a semiconductor substrate without any defects thereon. More particularly, this invention relates to inspection of a semiconductor substrate during manufacturing of high-density semiconductor devices with submicron features.
2. Description of the Related Art
Current demands for high performance associated with very large scale integration (VLSI) and ultra large scale integration (ULSI) require smaller submicron feature sizes, faster speeds, denser components and improved reliability. Fabrication of integrated circuits (IC) having multiple levels of patterned metallization lines and interconnects which are separated from one another by interlayer dielectrics to form features, e.g., vias, trenches, holes, plugs, wires, lines, contacts, dies and, studs, etc., are prone to include defects thereon. For example, electromigration along a metal conductor during metal wiring may cause thinning or thickening of the conductor resulting in void and hillock formation, respectively, as well as damage to metallization lines and interconnects. Formation of various integrated circuits structures and device features with high precision and uniformity necessitates careful inspection to assure the reliability and functionality of the integrated circuits. However, the inspection equipment needed has become ever more complex and expensive.
Various inspection techniques for detecting defects include scanning electron microscopy (SEM) on semiconductor surfaces and cross sections, and thermal measurement analysis of a semiconductor die with lasers. However, these techniques are destructive to the features formed on a semiconductor substrate, time-consuming to perform, and thus may not be suitable during semiconductor manufacturing for defect detection.
Conventionally, metal wiring reliability is tested after the IC devices are fabricated (wafer-level testing) or packaged (packaging-level testing). Various reliability tests and burn-in scheduling tests, such as median time to failure (MTF) test, temperature ramp resistance analysis to characterize electromigration (TRACE), and various package-level and wafer-level electromigration acceleration tests, can be used to detect malfunctions or complete failure of the manufactured integrated circuits. These electromigration (EM) tests generally subject tested samples to relatively high stresses, such as forcing constant high current or high temperature to the tested samples, which are very destructive and are very time-consuming to perform, typically on the order of several hours to days or weeks, in order to predict a time that the tested samples will fail by extrapolating obtained information into years. In addition, the unique structures utilized on wafer-level testing to evaluate the result of stress can also cause failure of the IC. Further, the test structures occupy very small size between dies or vias which may have low defect density, thus are not sensitive enough to represent defect density prior to costly and time-consuming burn-in schedules of the integrated circuits.
Other conventional reliability tests which are relatively quick and non-destructive are based on noise measurement, e.g., correlating the occurrence of electromigration and stress voiding under aluminum wire or tungsten vias. Metal wiring reliability using a noise spectrum is generally limited to packaged ICs and has not yet been implemented during processing of thin film deposition or planarization prior to fabricating integrated circuits and packaging into integrated circuit devices. Also, noise measurement on copper wire structures was not successful, partly due to the presence of interface void formation between materials of poor adhesion with each other on a small device active area. In addition, direct application of electrical probes on the ever small semiconductor structures during manufacturing are prone to errors caused by background noise.
Therefore, there is a need for inspection of a semiconductor substrate while it is still inside a substrate processing system to look at reliability and quality of features formed on the semiconductor substrate before costly and time-consuming testing on fabricated and/or packaged integrated circuits.